versys design

Design Services

IP Specification Development
Design Architecture and Partitioning
Front End Design Implementation (RTL)
IP Core Integration
Design For Power Architecture
Logic Synthesis
Static / Dynamic timing analysis
Equivalence checking
Power Analysis
Test Pattern Generation
Fault Simulation
SoC DFT Architecture

Verification Services

Verification/Test Plan Development
Design Verification Environment Development
High-level modeling
Coverage driven verification
Corner-cases extraction and testing
Formal Verification
Test Environment Development
Fault Simulation & ATPG
DFT & Test vector generation

© 2017 versysdesign.